Combinational and Sequential Digital Circuit Design
Overview
Digital logic design constitutes the architectural foundation of every programmable system in modern electrical engineering, from microcontrollers in embedded protection relays to the FPGAs that implement real-time phasor measurement unit (PMU) algorithms. This project covers the full combinational-to-sequential design arc: starting from Boolean algebra and Karnaugh-map minimization of combinational functions, through the design and timing analysis of storage elements, and culminating in the implementation of a finite state machine (FSM) capable of detecting a specified binary sequence in a serial bitstream. All circuits were implemented physically on logic trainer boards using 74-series TTL integrated circuits, not merely simulated, tying abstract design methods to observable hardware behavior.
The project was structured as a progressive series of sub-experiments, each introducing one new design concept while building on previously verified circuits. This progression — combinational logic, then arithmetic, then memory elements, then sequential machines — mirrors the canonical structure of digital systems textbooks and maps directly onto the hardware hierarchy from gates to processors.
Technical Approach
The combinational logic suite began with a 4-to-1 multiplexer designed from first principles: the truth table expressed the output as a sum of minterms, a 4-variable Karnaugh map reduced the expression to a minimal sum-of-products form, and the minimized Boolean expression was implemented with 74LS08 AND gates, 74LS32 OR gates, and 74LS04 inverters. A 7-segment display decoder followed, mapping 4-bit BCD inputs to the seven segment drive lines for numerals 0–9. The decoder's truth table has 16 rows (ten valid and six don't-care input combinations), and don't-care entries on the Karnaugh map enabled significant gate count reduction relative to a straightforward minterm expansion. The physical circuit drove a common-cathode LED display and was verified against all ten valid BCD codes. A 4-bit ripple-carry adder/subtractor used the 74LS83 4-bit full-adder IC, with XOR gates (74LS86) on the B-inputs to conditionally invert them for two's-complement subtraction when a mode select line is asserted — demonstrating that subtraction reduces to addition in two's-complement arithmetic.
The sequential logic suite introduced D and JK flip-flops using the 74LS74 and 74LS76 ICs respectively. Characteristic equations (Q⁺ = D for the D flip-flop; Q⁺ = J·Q' + K'·Q for the JK) were derived from excitation tables and verified by clocking each device through a known input sequence and recording Q and Q' at each rising edge against predicted values. Setup time (t_su = 20 ns) and hold time (t_h = 5 ns) constraints were identified from the datasheet and respected in the test clock frequency selection. A 4-bit synchronous binary counter was constructed from four JK flip-flops by solving the JK excitation equations for each bit position from the counter's state transition table: J₀ = K₀ = 1, J₁ = K₁ = Q₀, J₂ = K₂ = Q₀·Q₁, J₃ = K₃ = Q₀·Q₁·Q₂. The synchronous architecture was chosen explicitly over a ripple counter to eliminate accumulated propagation delay that would cause transient glitch states at higher clock frequencies.
The most complex sub-experiment was a Mealy-model FSM designed to detect the sequence "1011" in a serial bitstream, asserting an output Z = 1 for one clock cycle upon recognizing the last bit of the pattern. The design proceeded through state diagram construction (five states including reset), state table derivation, state assignment, and JK flip-flop excitation equations using Karnaugh-map minimization per state variable. The assembled FSM was tested by clocking in an 18-bit test sequence containing three embedded "1011" patterns — at positions 4, 9, and 15 — and confirming Z asserted exactly at those clock cycles with no spurious assertions at any other position.
Project Gallery
Outcomes & Learnings
All circuits met their functional specifications when verified against truth tables and timing diagrams. The synchronous counter operated correctly at the 1 MHz test clock frequency with no glitch states, validating the synchronous architecture choice over a ripple design that would have produced 15 ns of accumulated propagation delay — sufficient to cause output glitches if decoded combinationally. The sequence detector produced Z assertions at all three expected positions in the 18-bit test stream with zero false positives, confirming the state machine design and the JK excitation equation derivations.
Three design skills developed in this project formed the direct foundation for subsequent graduate-level work. First, Karnaugh-map minimization and state machine design recur in programmable logic contexts: the mental model of minimizing Boolean expressions transfers directly to synthesizing VHDL or Verilog for FPGA implementation of protection algorithms. Second, the discipline of verifying sequential circuits against timing diagrams — checking setup and hold violations before increasing clock frequency — establishes the habits of mind needed for high-speed digital design in microprocessor and DSP-based relay platforms. Third, the physical implementation on TTL hardware, rather than simulation alone, made propagation delay, fanout loading, and power supply decoupling tangible and measurable rather than abstract datasheet numbers.
The FSM sequence detector, in particular, is a microcosm of pattern recognition in digital systems: the same state-machine formalism that detects "1011" in a bitstream underlies the protective relaying algorithms that detect fault signatures in sampled current waveforms, the communication protocol parsers that frame serial data in IEC 61850 GOOSE messages, and the event detectors in phasor measurement units that flag frequency excursions in real time. This conceptual continuity between undergraduate gate-level design and graduate power system protection research made the digital circuit design project among the most consequential of the undergraduate curriculum.