System Design Using 8086 Microprocessor
Overview
This project designed and implemented embedded programs and hardware interfaces for the Intel 8086 16-bit microprocessor. The work spans assembly-language programming, memory interfacing, and peripheral control, building foundational competency in low-level system design at the register and bus level.
The 8086 occupies a unique pedagogical position: its segmented memory model and real-mode operation expose students directly to the address bus, data bus, and control signal interactions that higher-level abstractions conceal. Engaging with the processor at this level establishes an accurate mental model of how software commands translate into physical bus cycles — a model that remains relevant in embedded and power-electronics control contexts where register-level firmware is standard practice.
Technical Approach
Programs were written in 8086 assembly language using the full 8086 instruction set. Five programs spanned arithmetic routines (multi-precision addition and multiplication using the MUL and IMUL opcodes), string operations (block move and string comparison using SI/DI register pairs with REP prefix), and interrupt service routines (ISR installation via the interrupt vector table at segment 0000h, with IRET termination). Each program was assembled with a two-pass assembler and loaded into the emulator's simulated RAM for execution tracing.
The hardware interface design used 74-series ICs to implement memory decode logic: a 74LS138 three-to-eight decoder mapped the upper address lines to ROM and RAM chip-select signals, dividing the 1 MB address space into fixed blocks. I/O port interfacing used the 8255 Programmable Peripheral Interface, configured in Mode 0 for basic I/O with port direction set by the control word register. A 7-segment display driver connected to Port A of the 8255, with a software lookup table translating BCD-coded digits to the seven segment patterns required by a common-cathode display.
Simulation in an 8086 emulator preceded hardware verification on a development board. The emulator's single-step mode allowed register contents and flag states to be inspected after each instruction, confirming that flag manipulation (carry, auxiliary carry, overflow) behaved as specified before committing the program to hardware testing.
Outcomes & Learnings
All five programs were successfully implemented and tested: arithmetic routines produced correct results across boundary conditions including carry propagation and signed overflow; string programs moved and compared data blocks of arbitrary length without off-by-one errors; and the ISR correctly saved and restored the processor context, confirmed by stack inspection before and after the interrupt sequence.
The display driver correctly decoded BCD-to-7-segment mapping for all ten digits (0–9), with each segment state verified against the display datasheet truth table. Hardware testing confirmed that the 74LS138 decode logic assigned non-overlapping address regions to ROM and RAM without bus contention.
The project established competency in assembly-language programming and hardware-software co-design at the register level. This low-level fluency directly supports subsequent embedded systems work where microcontroller peripheral registers — timers, ADCs, communication interfaces — must be configured by writing to specific memory-mapped addresses, a pattern identical in structure to the 8086 I/O port scheme implemented here.
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